You are hereReSoNoC project

ReSoNoC project

Reconfiguration Solution in Designing Network-on-Chip Architectures (ReSoNoC)

Thanks to the rapid evolution of semiconductor technology, designers integrate more and more processing units (i.e., Intellectual Properties or IPs) into a System-on-a-Chip (SoC) to meet the high demand of new applications. A globally shared bus cannot meet the increasing demand of on-chip communication for exchanging data between IP cores and the system design encounters many problems such as clock skew, limited throughput, power efficiency, scalability and flexibility. The Network-on-Chip (NoC) paradigm has been emerging as a promise solution for the on-chip communication in complex SoCs. The advantages of a NoC based architecture are numerous: high scalability and versatility, high throughput with good power efficiency. Many research groups (research centers, universities, industries) have initiated many research activities on NoCs, even 3D integration of NoCs, but there are still a lots of aspects need to be addressed to bring the NoC paradigm to commercial products, particularly, reconfiguration and optimization solutions for NoC architectures. In this research proposal, we will investigate to reconfiguration solutions, which support dynamically reconfiguring the NoC architecture, to meet the requirements of target applications, especially, in terms of communication throughput, fault tolerance, and power consumption. To do that, the project will address a set of problems such as hardware design of NoC architectures (routers, interfaces, and topologies), routing algorithms and network protocols, application mapping, etc. to propose an efficient reconfiguration solution for designing NoCs. The proposed solution will be then validated in a developed NoC platform for proving its efficiency before being used.

This research aims at developing a reconfigurable NoC platform for designing NoC based systems. Therefore, the project includes the following main goals:

  • Investigate to NoC paradigm and develop a NoC platform for simulating and analyzing different parameters of NoC architectures.
  • Investigate and develop a global reconfiguration solution for NoC design, which will be applied for future NoC based systems. The proposed reconfiguration solution should be able to resolve the appearance of defects/faults in the system in order to guarantee the correct operation of the system. In addition, the solution should be used to manage effectively network resources as well as power consumption.


Key members:

  1. Xuan-Tu Tran, Principal Investigator
  2. Duy-Hieu Bui
  3. Nam-Khanh Dang
  4. Minh-Trien Pham
  5. Kiem-Hung Nguyen
  6. Thanh-Vu Le Van, PhD student

Publications (selected):

  1. Hung K. Nguyen, Thanh-Vu Le-Van, Xuan-Tu Tran. A Survey on Reconfigurable System-on-Chips. REV Journal on Electronics and Communications (JEC), 2017, ISSN: 1859-387X.
  2. Thanh-Vu Le-Van. Reconfigurable Network-on-Chip Solution for Complex Systems. PhD thesis. Last defensed on December 21, 2017.
  3. Thanh-Vu Le-Van, Xuan-Tu Tran. High-Level Modeling and Simulation of a Novel Reconfigurable Network-on-Chip Router. REV Journal on Electronics and Communications (JEC), pp. 68-74, Vol. 4, No. 3-4, July-December, 2014, ISSN: 1859 – 387X.
  4. Nam Khanh Dang, Akram Ben Ahmed, Xuan Tu Tran, Yuichi Okuyama, Abderazek Ben Abdallah. A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25 (11). pp. 3099-3112. ISSN 1063-8210. (SCI)
  5. Nam-Khanh Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, Xuan-Tu Tran. Soft-Error Resilient 3D Network-on-Chip Router. The IEEE 7th International Conference on Awareness Science and Technology (IEEE iCAST 2015), 22-24 September 2015, Qinhuangdao, China.
  6. Van-Nam Dinh, Hung K. Nguyen, Minh-Trien Pham, Xuan-Tu Tran. An IDPSO Algorithm-based Application Mapping Method for Network-on-Chips. In Proceedings of the 7th International Conference on Integrated Circuits, Design, and Verification (ICDV), pp. 104-110, Hanoi, Vietnam, 5-6 October 2017, ISBN: 978-1-5386-3377-9.
  7. Hung K. Nguyen, Quang-Vinh Tran, Xuan-Tu Tran. Data Locality Exploitation for Coarse-grained Reconfigurable Architecture in Reconfigurable Network-on-Chips. In Proceedings of the 5th International Conference on Integrated Circuits, Design, and Verification (ICDV 2014), pp. 75-81, Hanoi, November 2014, ISBN: 978-4-88552-294-9.
  8. Xuan-Tu Tran, Tung Nguyen, Hai-Phong Phan, Duy-Hieu Bui. AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E100-A, No.8, pp. 1650-1660, Aug. 2017, ISSN: 1745-1337. (SCIE)
  9. Thi-Thuy Nguyen, Xuan-Tu Tran. A Novel Asynchronous First-In-First-Out Adapting to Multisynchronous Network-on-Chips. In Proceedings of the 7th International Conference on Advanced Technologies for Communications (ATC 2014), pp. 365-370, Hanoi, Vietnam. ISBN: 978-1-4799-6955-5.
  10. Thi-Thuy Nguyen, Thanh-Vu Le-Van, Kiem Hung Nguyen, Xuan-Tu Tran. Routing-path Tracking and Updating Mechanism in Reconfigurable Network-on-Chips. In Proceedings of the 2016 IEEE International Conference on Integrated Circuit Design and Technology, 27-29 June 2016, Ho Chi Minh city, Vietnam.
  11. Hai-Phong Phan, Xuan-Tu Tran. Design and Modeling of a Voltage-Frequency Controller for Network-on-Chip Routers base on Fuzzy-Logic. VNU Journal of Computer Science and Communication Engineering (JCSCE), pp. 56-65, Vol. 31, No. 2, 2015, ISSN: 0866-8612.
  12. Hai-Phong Phan, Xuan-Tu Tran, Tomohiro Yoneda. Power Consumption Estimation using VNOC2.0 Simulator for a Fuzzy-Logic based Low Power Network-on-Chip. In Proceedings of the 2017 IEEE International Conference on Integrated Circuit Design and Technology, 23-25 May 2017, Texas, USA.
  13. Hai-Phong Phan, Xuan-Tu Tran. Fuzzy-Logic based Low Power Solution for Network-on-Chip Architectures. In Proceedings of the 2016 International Conference on Advanced Technologies for Communications, 12-14 October 2016, Hanoi, Vietnam.
  14. Hai-Phong Phan, Xuan-Tu Tran. A Fuzzy-Logic based Voltage-Frequency Controller for Network-on-Chip Routers. In Proceedings of the 11th Conference on PhD Research in Microelectronics and Electronics (IEEE PRIME 2015), Glasgow, Scotland, 29 June - 2 July, 2015.